The size of devices on semiconductor chips has decreased according to Moore's Law for more than 50 years. As features grow smaller, aspect ratios increase and device designs become more complex, new challenges arise in manufacturing such devices.
In recent years, there has been a shift toward the use of removable hardmask layers below resist films for patterning and etching of semiconductor substrates. Removable hardmasks offer advantages in reducing stack height and improving electrical properties of the final device, but as devices continue to shrink, residual stress engineered into hardmask layers to improve etch selectivity causes bending and weaving of pattern lines, line roughness, space width roughness, and general distortion of the etched pattern. In smaller features, such distortion increasingly causes device failure. Moreover, in some cases, residual stress in the hardmask layer causes problems with delamination during processing.
Thus, there is a continuing need for methods of etching fine patterns with minimal distortion in substrates for various applications in the semiconductor industry.